1. Technical Field
Various embodiments of the present disclosure relate to electro-static discharge (ESD) protection devices and, more particularly, to ESD protection devices having a low trigger voltage.
2. Related Art
In general, most semiconductor devices include ESD protection circuits, each of which is coupled between a signal pad or a data pad and a ground pad to protect inner circuits of the semiconductor devices. If the signal pad or the data pad of the semiconductor device is in contact with a charged human body or a charged machine, static electricity may be generated which produces a high voltage and the high voltage may be applied to the signal pad. In such a case, the ESD protection circuit connected to the signal pad may provide a bypass current path to prevent an inner circuit of the semiconductor device from being damaged. In development of micro-chips, a design technology of the ESD protection circuit becomes more and more important to protect the micro-chips from ESD stress and to provide highly reliable micro-chips. The ESD protection circuit may be referred to as ESD protection device.
A gate grounded N-type MOS field effect transistor GGNMOS device has been widely used as the ESD protection device. However, if the GGNMOS device is employed as the ESD protection device of a chip, it may be difficult to reduce a size of the chip since the GGNMOS device occupies a relatively large area. In general, a current tolerance value of the GGNMOS device is merely within the range of about 5 mA/μm to about 10 mA/μm. Thus, to meet an industrial standard value such as, 2 amperes of an ESD current, the GGNMOS device has to be designed to have a channel width of about 200 μm to about 400 μm. In addition, a drain region of the GGNMOS device has to be designed to have a relatively large area to obtain an excellent ESD characteristic of a chip. Accordingly, if the GGNMOS device is employed as the ESD protection device, there may be a limitation in designing highly integrated micro-chips.
Moreover, since the GGNMOS device used as the ESD protection device is coupled to a ground pad, the ESD protection device may exhibit a relatively high trigger voltage. If the trigger voltage of the ESD protection device is relatively high, a high voltage signal generated by static electricity may be transmitted to an inner circuit of the chip. As a result, the inner circuit of the chip may be damaged and may cause malfunction of the chip.